【 Weak current College 】 DDR3 and DDR2 difference

1, the number of logical Bank

DDR2SDRAM 8Bank 4Bank and in the design, the purpose is to meet future demand for bulk chips. Whereas DDR3 will probably start from 2Gb capacity, therefore the starting logical Bank is eight, and also for the future of 16 logical Bank ready.

2 packages (Packages)

DDR3 as new features, so in PIN will increase 8bit chip with 78-ball FBGA package, 16bit chip 96-ball FBGA package, but you have DDR2 60/68/84-ball FBGA package three kinds of specifications. And DDR3 must be green packaging, does not contain any harmful substances.

3, burst lengths (BL, BurstLength)

Because of the DDR3 prefetch to 8bit, burst cycle (BL, BurstLength) are also fixed for 8, while for DDR2 and DDR architecture early, BL = 4 is commonly used, DDR3 for this added a 4-bitBurstChop (sudden catastrophe) mode, i.e. from a BL = 4 read plus a BL = 4 writes to synthesize a BL = 8 data burst transfer, are available through A12 address line to control this burst mode. But it should be noted that any sudden disruptive actions are prohibited in DDR3 memory, and is not supported, replaced by more flexible burst transmission control (such as sudden 4bit order).

3. addressing timing (Timing)

Just like the change from the DDR and DDR2 to increase the number of delayed cycle, DDR3 CL cycle will also increase than DDR2. The scope of CL DDR2 is generally between 2 to 5, and DDR3 is between 5 and 11, and additional latency (AL) design also vary. When AL-DDR2 range from 0 to 4, and when AL DDR3 has three options, namely 0, CL-1 and CL-2. In addition, the new DDR3 also increases a timing parameters — write latency (CWD), this parameter will be depending on the operating frequency.

4. What's new-reset (Reset)

Reset is DDR3 new important features, and for this purpose specially prepared a PIN. DRAM industry has long ago would require increasing the feature, and now finally found in DDR3. This PIN makes the DDR3 initialization processing made simple. When the Reset command is valid, the DDR3 memory will stop all operations, and switch to a minimal activity State to conserve power. In the Reset period, DDR3 memory will close the inner most of the functionality, so there is data reception and dispatcher will close. All internal programs unit will reset, DLL (delay locked loop road) and the clock will stop working, and ignore any data on the bus. This will allow maximum savings power DDR3.

5, new features-ZQ calibration

ZQ is also a new PIN, the PIN is received on a 240 ohm low tolerance reference resistor. This PIN through a set of commands, by chip calibration engine (ODCE, On-DieCalibrationEngine) to automatically validate data output drive on-resistance and ODT end resistance values. When the system generates this directive, shall use the clock cycles (at power-up and after initialization using 512 clock cycle, the exit from the refresh operation with 256 clock cycle, in other cases with 64 clock cycles) on the on-resistance and resistance to recalibrate the ODT.

6, the reference voltage is divided into two

For memory system work very important reference voltage VREF, DDR3 system will be divided into two signals. One is to command and address signal service VREFCA, another is the data bus service VREFDQ, it will improve the system data bus-to-noise level.

7, according to the temperature automatic self refresh (SRT, Self-RefreshTemperature)

In order to ensure that the saved data is not lost, DRAM must be refreshed periodically, DDR3 is no exception. However, for the greatest savings in power, DDR3 introduced a new type of automatic self refresh design (ASR, AutomaticSelf-Refresh). When you start the ASR, through a built-in to the DRAM chip temperature sensors to control the refresh frequency, because the refresh frequency is high, with electricity, the temperature is increased. Which temperature sensor is to ensure that data is not lost, as far as possible reduce the refresh rate, lower operating temperature. Although DDR3 design of ASR is optional, and no market DDR3 memory support this feature, so there is an additional feature is the auto-refresh temperature range (SRT, Self-RefreshTemperature). Register through mode, you can choose between two temperatures, one is the normal temperature range (for example 0 ° c to 85 ° c), the other is the extended temperature range, such as up to 95 ° c. For DRAM internal setting of both temperature range, DRAM will be constant frequency and current refresh operation.

8. local self refresh (RASR, PartialArraySelf-Refresh)

This is an optional DDR3, through this function, the DDR3 memory chips can only refresh some logic Bank, and not refresh all, and thus minimize was a refresh of power consumption. Unlike the move-memory (MobileDRADesign M).

9, point-to-point connection (P2P, Point-to-Point)

This is to improve system performance and significant changes, it is also a crucial DDR2 system. In DDR3 system, a memory controller will only deal with a memory channel and the memory channel can only be one slot. Therefore, memory DDR3 memory controller and the module is a point-to-point (P2P, Point-to-Point) relations (single physical Bank of modules), or point-to-point (P22P, Point-to-two-Point) relations (dual physical Bank of modules), which greatly reduces the address/command/control and data bus load. In the memory module, and DDR2 category are similar, there are standard DIMM (desktop PC), SO-DIMM/Micro-DIMM (laptop), FB-DIMM2 (server), which will be adopted specifications of the second generation FB-DIMM higher AMB2 (Advanced memory buffer). However currently the DDR3 memory modules of the standard-setting work has just begun, pin design has not been finalized.