【 Weak current college 】 computer motherboards troubleshooting card code cross reference table (1)

00. display the configuration of the system; to be controlled INI19 boot mount.

01 processor test 1, processor status verification, if the test fails, the loop is infinite. Processor register test is about to begin, the Non-Maskable Interrupt will be deactivated. CPU register test in progress or failure.

02 confirmatory type (normal or manufacturing). If the keyboard buffer containing data to be invalidated. Deactivate the non-maskable interrupt; by delaying the start. Write/read CMOS is ongoing or malfunctioning.

8042 keyboard controller cleared 03, issue TESTKBRD command (AAH) power on delay is complete. ROMBIOS check parts are in progress or failure.

04 made 8042 keyboard controller reset and verify TESTKBRD. The keyboard controller test in soft reset/power. Programmable interval timer test in progress or failure.

05 if repetitive manufacturing test 1 to 5, you get the 8042 control state. Determined the soft reset/power; upcoming boot ROM. DMA on as preparation is in progress or failure.

06 the circuit chip for initial preparation, disable video, parity, DMA circuit chip, and clear the DMA circuit, all pages of the registers and CMOS shutdown bytes. Has boot ROM check sum calculated ROMBIOS, and check the keyboard buffer is cleared. DMA initial page register read/write test in progress or failure.

07 processor test 2, verification of the work of the CPU registers. ROMBIOS check sum normally, the keyboard buffer is cleared, the keyboard issue BAT (Basic assurance testing).

08 the CMOS timer for initial preparation, the normal update cycle timer. Issued to the keyboard commands, write to BAT BAT command. RAM update test in progress or failure.

09EPROM check sum and it must be equal to zero before passing. Verify the basic guarantee of the keyboard, then verify the test keyboard command byte. First 64KRAM testing is in progress.

0A to prepare for the initial video interface. Issue a keyboard command that is written to the byte code order bytes of data. First 64KRAM chip or cable failure, shift.

0B test 8254 channel 0. Write to the keyboard controller command byte that will be issued a PIN 23 and 24 of the blockade/unlock command. First 64KRAM odd/even logic failure.

0C test 8254 channel 1. Keyboard controller pin 23, 24; lockout/unlock NOP command has been issued. The first address line failure 64KRAN.

0D1, check the CPU speed to match the system clock. 2. check the control chip is programmed value set at the beginning. 3. video channel test, if it fails, then the Horn. NOP commands have been processed; then test CMOS shutdown register. First 64KRAM parity of failure

0E test CMOS shutdown bytes. CMOS shutdown register read/write test; will calculate the sum CMOS checks. Initialize input/output port address.

0F testing expansion of CMOS. The calculated sum CMOS checks written diagnosis bytes; CMOS begin initial preparation.

10 tests DMA channel 0. CMOS has made initial preparation, CMOS status register soon for the date and time for initial preparation. First 64KRAM bit 0.

11 tests DMA channel 1. CMOS status register has already made the initial preparation, is about to deactivate DMA and interrupt controller. First 64DKRAM 1 bit failures.

12 test DMA page registers. Deactivate DMA controller 1 and interrupt controller 1 and 2; upcoming video monitor and make the initial port B. First 64DKRAM 2nd failure.

13 test 8741 keyboard controller interface. Video monitor is deactivated, port B has to make initial preparations; upcoming circuit chip initialization/storage automatic detection. First 64DKRAM 3rd failure.

14 test memory update trigger circuit. Circuit chip initialization/storage service automatically detects the end; 8254 timer test is about to begin. First 64DKRAM 4th failure.

15 test begins with 64 k system memory. 2 channel timer test by half; 2nd channel 8254 timer is completing a test. First 64DKRAM 5th failure.

16 the establishment 8259 interrupt vector table. 2 channel timer at the end of the test; 8254 timer: 1 channel is about to complete the test. First 64DKRAM 6th failure.

17 tuneup video input/output, if equipped with a video BIOS is enabled. 1 channel timer at the end of the test; 8254 timer 0 channel is about to complete the test. First 64DKRAM 7th by failure.

18 test video memory, if you install the optional video BIOS pass, you can bypass. No. 0 channel timer at the end of the test; the upcoming update storage. First 64DKRAM 8th bit failures.

19 test 1 channel interrupt controller (8259) shielding. Has begun to update the memory, then the update will be completed memory. First 64DKRAM 9 th.

1A test 2 channel interrupt controller (8259) shielding. Is triggered, the memory update line check 15 microseconds pass/break time. The first 10-bit 64DKRAM.

1B test the CMOS battery level. Complete storage update30 microseconds between testing; upcoming Basic 64 k memory test. First 64DKRAM 11th failure.

1C test sum CMOS checks.. first 64DKRAM 12 bit failures.

1D set CMOS configuration.. first 64DKRAM 13 bit failures.

1E determination system memory size and put it and CMOS value comparisons.. first 64DKRAM 14 bit failures.

1F test 64K storage to a maximum of 640K.. first 64DKRAM 15 bit failures.