【School】 understand the weak no one would dare you Huyou CPU (1).

<br> 1. <BR> GHz clock frequency, also called, in units of MHz, is used to indicate CPU operation speed. .The frequency = CPU FSB × multiplication factor. .Many people think that CPU frequency to determine the running speed, this is not just a one-sided, and the server is concerned, this understanding has gone wrong. .So far, there is no formula to achieve a certain frequency and the actual speed of operation of the numerical relationship between the two, even two processor manufacturers Intel and AMD, at this point there are a lot of controversies, from the Intel .the development trend of products, you can see Intel is focused on strengthening the development of its own frequency. .Like other processor manufacturers, some people have won the Transmeta 1G to do a quick comparison, and its efficiency is equivalent to 2G of Intel processors. .<BR> <BR> Therefore, CPU's frequency and the actual computing power of CPU is not directly related, in CPU frequency, said digital pulse signal within the shock speed. .In Intel's processors, we can also see examples of this: 1GHzItanium chip can behave almost as fast with 2.66GHzXeon/Opteron or 1.5GHzItanium2 about as fast as with the 4GHzXeon/Opteron. .CPU CPU operation speed depends on various aspects of the pipeline's performance. .<BR> Course, the frequency and the actual speed of operation is concerned, can only say that frequency is only one aspect of CPU performance, and do not represent the overall CPU performance. .<BR> <BR> 2. <BR> FSB CPU FSB is the reference frequency, the unit is MHz. . CPU FSB motherboard determines the speed block. .Plainly, in the desktop machine, we are talking about overclocking, CPU FSB is over (of course under normal circumstances, CPU's multiplier is locked) I believe this is well understood. .But in terms of server CPU, overclocking is absolutely not allowed. .Speaking in front of the motherboard CPU determines the speed, the two are running in parallel, if the server CPU overclocking, and changing the FSB, will generate an asynchronous operation, (a lot of desktop motherboards support asynchronous operation) that would cause the entire .server system instability. .<BR> <BR> Most current computer system memory and the motherboard FSB is running between the synchronous speed, in this way can be understood as memory, CPU FSB directly connected to pass, to achieve between .synchronous operation. .FSB and the front-side bus (FSB) frequency can easily be confused, the following front-side bus to talk about our difference between the two. .<BR> <BR> 3. Front side bus (FSB) frequency <BR> front side bus (FSB) frequency (the bus frequency) is a direct impact on CPU and memory speed of direct data exchange. .There is a formula to calculate that the data bandwidth = (bus frequency × data bandwidth) / 8, the maximum bandwidth of data transfer depends on the simultaneous transmission of data of all the width and transmission frequency. .For example, now supports 64-bit Xeon Nocona, front-side bus is 800MHz, in accordance with the formula, it is the maximum bandwidth of data transmission 6.4GB / sec. . <BR> <BR> FSB and the front-side bus (FSB) frequency difference: front-side bus speed refers to the data transmission speed between the FSB is the CPU running in parallel with the motherboard speed. .In other words, 100MHz FSB especially digital pulse signal in shock ten million times per second; and 100MHz front side bus CPU per second refers to the amount of acceptable data is 100MHz × 64bit ÷ 8Byte/bit = 800MB / s .. .<BR> <BR> Fact, "HyperTransport" the emergence of structure, so that the actual sense of the front-side bus (FSB) frequency change. .Prior to IA-32 architecture we know must have three important components: Memory Controller Hub (MCH), I / O Controller Hub and PCIHub, as is typical Intel chipset Intel7501, Intel7505 chipset for dual Xeon processor capacity .a tailored, they contain MCH provides for the CPU front side bus frequency is 533MHz, with DDR memory, front side bus bandwidth of up to 4.3GB / sec. . However, with increasing processor performance to the system architecture also brings many problems. .The "HyperTransport" architecture not only solves the problem, and more effectively improve the bus bandwidth, for example AMDOpteron processor, flexible HyperTransportI / O bus architecture, it integrates the memory controller, the processor chip does not pass through the system bus .group to exchange data directly, and memory. .In this case, front-side bus (FSB) frequency of the processor does not know where in the AMDOpteron talked about. .<BR> <BR> 4, CPU's bit and word length <BR> bit: in digital circuits and computer techniques used in binary code only "0" and "1", where both the "0" or "1" .In the CPU, is a "bit." .<BR> Word: computer technology in the unit of CPU time (same time) to process a number of binary digits called the word length. .They are able to handle 8-bit data word length is usually called 8-bit CPU CPU. .Similarly, 32-bit CPU can handle per unit time in the 32-bit word length binary data. .The difference between byte and word length: the commonly used English characters with 8 bits can represent, and are usually referred to as a byte will be 8. .Word length is not fixed, for different CPU, not the same word length. .8-bit CPU can only handle one byte, and a 32-bit CPU can handle 4 bytes, the same way for 64-bit word length of a CPU can process 8 bytes. .<BR> <BR> 5. <BR> Multiplier factor multiplier factor is the CPU FSB frequency and the relative proportions. .At the same FSB, the multiplier the higher the frequency the higher the CPU. .But in fact, the premise of the same FSB, the high frequency of the CPU itself significance. .This is because the data transfer between CPU and system speed is limited, the blind pursuit of high-frequency and high frequency of the CPU will be significant "bottleneck" effect-CPU to get data from the system to meet the CPU speed does not limit operation .speed. .In addition to projects like the general version of the Intel CPU is multiplier locked, and AMD did not lock before the <BR> 6. <BR> Buffer cache size is an important indicator of the CPU, and cache structure and the size of the CPU .the impact of very large speed, CPU cache to run in high frequency, usually with frequency and processor operating efficiency far greater than the system memory and hard drive. .Actual hours of work, CPU is often need to repeat the same data blocks read, and cache size increases, the CPU can greatly improve the hit rate of the internal read data, without memory or hard disk and then to find, in order to improve system performance .. .However, due to CPU chip area and cost factors to consider, the cache is very small. .<BR> <BR> L1 Cache (cache) is the CPU cache, the first layer is divided into data cache and instruction cache. .Built-in L1 cache size and structure of the greater impact on the performance of CPU, but by the static RAM cache composition, structure more complex, the CPU die area can not be the case too, L1 cache capacity level .can not do too much. .General server CPU's L1 cache size is usually in the 32-256KB. .<BR> L2 Cache (secondary cache) is the CPU's second level cache, both internal and external sub-chip. .Internal chip secondary cache same speed and frequency, while the external secondary cache is only half the frequency. .L2 cache size will also affect the CPU's performance, the principle is the bigger the better, and now the family is the biggest with the CPU capacity of 512KB, and the server and workstation CPU's L2 cache with as much as 256-1MB, 2MB or 3MB, some as high as .. .<BR> <BR> L3 Cache (three-levelcache), divided into two types, early is external, and now are built. .The practical effect of it is, L3 cache memory, applications can further reduce latency and increase the large amount of data processor performance calculation. .Lower memory latency and improve computing power for large data games are helpful. .The L3 cache in the server space to increase performance is still significantly improved. .For example, the configuration with a larger L3 cache will be more effective use of physical memory, so it is relatively slow disk I / O subsystem can handle more data requests. .Processor with a larger L3 cache file system to provide more efficient caching behavior and the short message and processor queue length. .<BR> <BR> In fact, the first L3 cache is used in AMD's K6-III processor, when the L3 cache is limited by manufacturing processes, and have not been integrated into the chip, but integrated on the motherboard. .In the only system bus frequency can be synchronized and L3 cache with main memory in fact little different. .Later, using the L3 cache, Intel introduced the Itanium server processor market. .Next is the P4EE and Xeon MP. .Intel also plans to launch a 9MBL3 cache Itanium2 processor, and later 24MBL3 cache dual-core Itanium2 processors. .<BR> <BR> But basically L3 cache on the processor performance improvement seems not very important, for example, with 1MBL3 cache XeonMP Opteron processor is still not the opponent, we can see the increase in FSB than the increase with the cache .to more effective performance. .<BR> <BR> 7.CPU <BR> CPU instruction set extensions to rely on instructions to calculate and control systems, each CPU in the design was subject to a series of hardware compatible with its instruction. .CPU instruction is also an important indicator of the strength, the microprocessor instruction set is to improve the efficiency of one of the most effective tools. .At this stage about the mainstream architecture, instruction set can be divided into complex instruction set and reduced instruction set of two parts, as seen from the concrete, such as Intel's MMX (MultiMediaExtended), SSE, SSE2 (Streaming-Singleinstructionmultipledata-Extensions2), SEE3 .and AMD's 3DNow! are all extended CPU instruction set, respectively, enhance the CPU's multimedia, Internet and other images and graphics processing power. .We are usually called the CPU instruction set extensions "CPU's instruction set." .SSE3 instruction set is currently the smallest instruction set includes 57 previously ordered MMX, SSE contains 50 commands, SSE2 contains 144 commands, SSE3 includes 13 commands. .Currently the most advanced SSE3 instruction set support for Intel Prescott processor has SSE3 instruction set, AMD dual-core processors in the next to join them on the SSE3 instruction set support, Transmeta's processors will also support this instruction set. .<BR> <BR> 8.CPU core and I / O voltage <BR> start from 586CPU, CPU's core voltage and the voltage is divided into I / O voltage of the two, usually less than or equal CPU core voltage I / O .voltage. .Which is based on the size of core voltage CPU production process, are generally the smaller the production process, the lower the core voltage; I / O voltage is generally in the 1.6 ~ 5V. .Low-voltage power too large and can solve the problem of high heat. .<BR> <BR> 9. <BR> Manufacturing process micron manufacturing process within the IC is the distance between the circuit and the circuit. .Trends in the manufacturing process is to the direction of higher intensity. .The higher density of IC circuit design, means that the size of the area in the same IC, you can have a higher density, more complex circuit design. .Now the main 180nm, 130nm, 90nm. .Officials have recently expressed a 65nm manufacturing process. .<BR> 10. Instruction set <BR> <BR> (1) CISCinstruction set <BR> CISC instruction set, also known as complex instruction set, the English name is CISC, (ComplexInstructionSetComputer abbreviation.) .In CISC microprocessors, the program order of each instruction is serial execution, each instruction in the serial order of each operation is also performed. .Sequence has the advantage of simple control, but the utilization of the various parts of the computer is not high, the implementation is slow. .In fact, it is the Intel x86 series of production (that is IA-32 architecture) CPU and compatible CPU, such as AMD, VIA's. . Even now since the new X86-64 (also as AMD64) belong to the CISC category. .<BR> <BR> To know what is the instruction set but also from today's X86 architecture CPU start. .Intel X86 instruction set is the first one of its 16-bit CPU (i8086) specially developed, IBM1981 launched the world's first PC, the CPU-i8088 (i8086 Starter Edition) X86 instruction is used, while the computer to improve .floating-point data processing capacity increased by X87 chip, the future will be X87 X86 instruction set and instruction set referred to as X86 instruction set. .<BR> While technology continues to evolve as the CPU, Intel have developed a newer i80386, i80486 until the past PII Xeon, PIII Xeon, Pentium3, and finally to today's Pentium4 series, Xeon (not including the Xeon Nocona .), but to ensure that the computer can continue to run past the development of various applications to protect and inherit the wealth of software resources, so the production company for all Intel CPU still continue to use the X86 instruction set, so the CPU is still in its X86 series. .As IntelX86 series and compatible CPU (such as AMDAthlonMP,) X86 instruction set is used, so today the formation of a large series and is compatible X86 CPU lineup. .x86CPU present, there are intel server CPU and AMD's server CPU types. .<BR> <BR> (2) RISC instruction set <BR> RISC is in English "ReducedInstructionSetComputing" abbreviation, the Chinese meaning is "reduced instruction set." .It is based on the CISC instruction set developed, some of the CISC machine tests show that the use of the frequency of various instructions very poor, the most commonly used are relatively simple instructions, they accounted for only 20% of total orders, .but appear in the program accounted for 80% of the frequency. .Complex instruction set will increase the complexity of microprocessors, the processor's development time, high costs. .And complex instructions require complex operations, will inevitably reduce the speed of the computer. .For these reasons, the 20th century, was born 80 RISC-type CPU, as opposed to CISC-based CPU, RISC-type CPU not only streamline the command system, also used a technique called "superscalar and super-pipelined structure," greatly increased the ability of parallel processing .. .RISC instruction set is the development direction of high-performance CPU. .With the traditional CISC (complex instruction set) relative. .In contrast, RISC instruction format unification, type less, addressing less than the complex instruction set. .Of course, the processing speed to increase a lot. .Now widely used in high-end server, the directive system CPU, especially the high-end servers using RISC instruction set all the CPU. .RISC instruction set is more suitable for high-end server operating systems UNIX, Linux now also belong to similar UNIX operating system. .RISC-based CPU with Intel and AMD CPU in software and hardware are not compatible. .<BR> <BR> Present in the high-end servers using RISC CPU instructions are the following categories: PowerPC processor, SPARC processor, PA-RISC processors, MIPS processors, Alpha processors. .<BR> <BR> (3) IA-64 <BR> <BR> EPIC (ExplicitlyParallelInstructionComputers, exactly parallel instruction computer) is a RISC and CISC systems is the successor to have a lot of debate, EPIC system alone, it .into the RISC processors like Intel's system is an important step. .In theory, EPIC system designed CPU, in the same host configuration, the processing of applications than Windows-based applications under Unix is much better. .<BR> <BR> Intel server technology with EPIC Itanium CPU is Itanium (codenamed the Merced). .It is 64-bit processors, IA-64 series is the first. .Microsoft has also developed a code for the Win64 operating system, software to support it. .Used in the Intel X86 instruction set, it seems to turn to the more advanced 64-bit microprocessor, Intel to do so because they want to get rid of the x86 architecture huge capacity, so as to bring energetic and powerful instruction .set, then using EPIC instruction set IA-64 architecture was born. .IA-64 in many ways, than the x86 has made substantial progress. .IA32 breaks through the traditional structure of many of the limitations in the data processing capability, system stability, security, availability, considerable reason so to obtain a breakthrough improvement. .<BR> <BR> IA-64 microprocessor biggest flaw is their lack of compatibility with the x86, and Intel IA-64 processors in order to better software to run the two dynasties, which IA-64 processors . (Itanium, Itanium2 ... ...) introduced the x86-to-IA-64 decoder, thus able to translate x86 instructions to IA-64 instructions. .This decoder is not the most efficient codec, nor is it the best way to run x86 code (the best way is to run directly on the x86 processor x86 code), the Itanium and Itanium2 running the x86 application performance when .very bad. .X86-64 that became the root causes. .<BR> <BR> (4) X86-64 (AMD64/EM64T) <BR> <BR> AMD designs, can be handled at the same time, 64-bit integer arithmetic, and compatible with X86-32 architecture. .Which supports 64-bit logical addressing, while providing 32-bit addressing options converted; but the data manipulation instructions default to 32-bit and 8-bit, providing conversion into 64-bit and 16-bit option; support for general-purpose registers, if it is 32-bit .computing operations, the results should be extended into a full 64-bit. .This instruction has "direct execution" and "conversion implementation," the difference, the instruction field is 8-bit or 32-bit, to avoid the field too long. .<BR> <BR> X86-64 (also known as AMD64) production is not groundless, x86 processor, 32bit address space limited to 4GB of memory, while the IA-64 processors can not compatible with x86. .AMD fully consider the needs of customers, strengthening the function of x86 instruction set, so this instruction set can simultaneously support 64-bit computing model, so the structure of them is called AMD x86-64. .Technically AMD x86-64 architecture in order to carry out 64-bit computing, AMD introduced its new general-purpose registers of the R8-R15 as the expansion of the original X86 processor registers, but in the 32-bit environment is not entirely .use these registers. .The original registers such as EAX, EBX also expanded by 32 to 64 bits. .SSE unit in the newly added 8 new registers to provide support for SSE2. .Increase in the number of registers will bring performance improvements. .At the same time, in order to support both 32 and 64-bit code and registers, x86-64 architecture allows the processor to work in two modes: LongMode (long mode) and LegacyMode (genetic pattern), Long mode is divided into two sub-modes ( .Compatibilitymode 64bit mode and compatibility mode). .The standard has been introduced in the AMD Opteron processor in the server processor. .<BR> <BR> Also launched this year to support 64-bit EM64T technology, and then not yet been formally appointed as the EM64T until IA32E, that Intel is the name of 64-bit extension technology, to distinguish the X86 instruction set. .Intel's EM64T 64-bit sub-mode, and AMD's X86-64 technology is similar to a 64-bit flat linear addressing, adding eight new general-purpose registers (GPRs), also added support for SSE instructions 8 registers. .Similar with AMD, Intel's 64-bit technology will be compatible with IA32 and IA32E, only 64-bit operating system run time, it will be used IA32E. .IA32E will be composed of two sub-mode: 64-bit sub-mode and 32-bit sub-mode, as with the AMD64 is backward compatible. .Intel's EM64T will be fully compatible with AMD's X86-64 technology. .Nocona processors have now added some 64-bit technology, Intel's Pentium4E processors also support 64-bit technology. .<BR> <BR> Should be said that both are x86-compatible 64-bit microprocessor instruction set architecture, EM64T and AMD64, but there are some not the same place, AMD64 processors, the NX-bit processor in the Intel .will not provide..